1. Field of the Invention
The invention relates to a device for decoding encoded digital signals of the MPEG-type, comprising different modules including at least an audio module and a video module, provided for communicating with an external random-access memory via an interface module referred to as arbiter and intended to control the different types of access --to a row of pixels, a row of the MPEG macroblock or a macroblock in fields of opposite parity--to decoded images.
2. Description of the Prior Art
The envisaged field of use concerns the storage of images decoded by an MPEG2 decoder in an external memory of the DRAM-type (Dynamic Random Access Memory). As is illustrated in FIG. 1, showing an MPEG2 decoder in a very diagrammatic form, different modules (M.sub.1, M.sub.2, M.sub.3, . . . ) in such a decoder access an external DRAM memory via a single interface module referred to as "arbiter". This memory particularly provides the temporary storage of the compressed data stream as well as the storage of decoded images. The arbiter, denoted ARB, controls access to this external memory for the assembly of decoder modules (access required by image blocks which are to read or write information in the memory). The different modules M1, M2, M3, etc. effect different types of access to the decoded images and particularly, as illustrated in FIG. 2 three types of access:
(A) scanning per row of image pixels (denoted BLP); PA1 (B) scanning per row of MPEG macroblock (denoted BLM); PA1 (C) access to a macroblock in a field of a given parity and to the corresponding macroblock in the field of the opposite parity, denoted APO (even field CP and odd field CI in FIG. 2). PA1 the luminance information of 4 macroblocks MB1i, MB2i, MB3i, MB4i of the odd field (denoted i) and the luminance information of 4 corresponding macroblocks MB1p, MB2p, MB3p, MB4p in the even field (denoted p); PA1 the chrominance information of 8 macroblocks of the odd field and the chrominance information of 8 corresponding macroblocks in the even field. PA1 access to the rows of macroblocks: 4 consecutive luminance macroblocks (8 for chrominance); PA1 access to the rows of pixels: 4*16=64 consecutive luminance pixels (64 for chrominance); PA1 access to the even/odd macroblocks: such an access is possible, because due to its construction, they are on the same page of the DRAM memory.
Addressing of the DRAM memories of the FPM-type ("Fast Page Mode"), mentioned, for example in Patent Application WO 95/31874, is realized as follows. The data are stored in words of 64 bits by separating the chrominance and luminance information. Stored in a page of the DRAM memory (=512 words of 64 bits), and as shown in FIGS. 3 and 4, respectively, are:
This organization allows the following types of access, without any page jumps:
However, this addressing only relates to current DRAM memories. Other types of memories, the SDRAM memories, described, for example in the document "Synchronous dynamic RAM", B. Prince et al., IEEE Spectrum, 29 (1992), Oct., nr. 10, pages 44 to 49 (these synchronous DRAM memories make use of one synchronous interface: the inputs and outputs of the data are clock-synchronized), seem to be used more and more as replacements, particularly because of their higher transfer speed.